| ID |
Date |
Author |
Subject |
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58
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Thu, 12.03.2026 15:35:49 |
D. Rybka | NIM splitter in TOF-R | On 2026.03.11 NIM splitter device for trigger signal was installed in TOF-R rack and connected to all TOF-R DRS crates.
The lemo cable from Trigger card to splitter was changed from 3ns to 4ns. |
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57
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Wed, 25.02.2026 13:36:53 |
B. Maksiak | DRS startup procedure | Sorry, it's in Polish. When I have more time, I will translate it and add pictures and schematics.
https://codimd.web.cern.ch/dE-nElxPSkWLD8FySISiOQ?both#
DRS startup
DRS crate assembly
- Backplane: The DRS crate comes without the backplane. It has to be screwed to the crate. When installing the backplane make sure about connecting power to proper buses. When connected, install the power supply and fan unit. Test it with power. Check for no power-related failures.
- Install support modules: J110, J111, J112
- J111 - gets trigger signal, eventID number, clear signal. Gets busy signals from J110 and J112, performs logical OR on them and sends back busy signal to the central trigger. External clock should be provided to this module. All signals are distributed over the backplane.
- J110 - performs logical OR from busy signals sent by DRS boards by the left side of the backplane and outputs the result to module J111. Gets sync signal for global timing synchronization and spreads it to backplane.
- J112 - performs logical OR from busy signals sent by DRS boards by the right side of the backplane and outputs the result to module J111.
Installation of DRS boards and tests
- Install DRS boards, remember about setting them proper boardID on rotary switches and configuring the jumpers (by default, no jumper should be set on the board, for more custom solutions use jumpers J7 and J8)
- If none of J7 and J8 jumpers set, connect clock signal to J111. If needed, connect sync to J110.
- Connect four LEMO cables with trigger/eventID/clear/busy signals to J111. Optionally, install Trigger Box to the same crate and provide LVDS signal from central trigger. (note 1: Trigger Box works correctly when two green LEDs shine; note 2: In case of TOF crates for DRS there is only one Trigger Box per two racks, so LEMO signals should be split by NIM fan-in fan-out modules; in case of L0 trigger signal, the splitting cables should be as short as possible; note 3: If everything is connected properly, then at power up J111 all green LEDs should be off and at least one red should be on).
When you are satisfied by the performance of all the crate, install it in its final rack. Update the database.
Start of DRS readout machines
DRS readout machines are Dell PowerEdge C6100. Before they are operational, we need to make sure they are manageable using BMC interface (it might become very useful). If TDAQ network is already active and the machines are powered, they should get their address of the -mgmt interface. If the address is pingable and one can use ipmitool to communicate with them, then we are ready for next steps. If there are problems with pinging, there might be a network connection problem (check cables) or the BMC might start malfunctioning. I don't know the reason, but they happen to lose their MAC address or just not responding to connection requests. The only solution is to replace the machine.
If the machine communicates properly. Make sure that the machine gets proper image through TDAQ network. At this moment, The Battle For 4 USB Ports starts.
- After the boot, check the number of USB ports using command
lsusb | grep Renesas . If you see 4 entries (ports), the job is done and you can switch the procedure to another machine. If not...
- Try rebooting the machine at least up to 5 times. After each try, check the number of ports. My experience is that the number of ports after each reboot can be pretty random, but if you can see maximum of two, then the USB expansion card might be broken and need replacement while if you can see maximum three then it is almost certain that at some point you will get four ports.
- If after many reboots there is still no 4 ports, the machine should be cooled. My another experience is that it is much easier to get 4 ports when the machine is not warmed up. There is a good method to bring the machine to TDAQ room which is intensively air-conditioned to 20 degrees and keep it there for at least several hours (one day is optimal).
- If, after all tries, you cannot get 4 ports, replace the expansion card.
Connecting DRS boards to their readout machines
If time is not an issue, it can be done in a step-by-step way. Make sure all readout machines are turned on. Turn on DRS crate with the boards installed, but not yet connected to readout machines. In this state they are in the reset mode and all of them should have LEDs turned on in the same way.
- If the LEDs are off, then the board is most probably not powered.
- If the LEDs are on in a different way than expected, then the firmware version in a given board might be different.
Start connecting boards one by one by plugging the USB 3.0 cable between it and the readout machine. After connecting, the board should say hello by blinking the LEDs in a programmed way. If the board does not perform the programmed blinking procedure, there might be (at least) one of following problems:
- The USB cable might be not connected enough firmly. Disconnect the cable in question from both ends, restart the DRS crate and push the both ends of cable to their according sockets firmly.
- Check the cable with another connection that was already proven to be correct. There is a known problem that the cable just fails and it needs a replacement.
- There might be a situation that the machine recognizes an USB port, but it does not work anyway. One can restart the PCI bus or load a new firmware to the USB card (see: https://na61-elog.cern.ch/DRS+logbook/50). At worst case, one may restart the machine (with the risk that after restart there will be random number of USB ports).
- Make sure that the module J111 in the DRS crate is working properly - among other responsibilities, the module brings down the reset signal from the boards connected to backplane.
When all boards in the crate are connected and tested, restart the DRS crate again and check that all boards say hello.
Readout test crate by crate
If time is not an issue, it is the most comfortable to perform the readout tests firstly on every DRS crate separately and only then on entire system with all crates reading out together. This chapter describes read out tests of a single crate. This step requires operational TDAQ network, or at least one gateway, supervisor, trigger computer, a buffer, couple of event builders and, obviously, DRS machines.
Update the drs-crates.yml file to correctly reflect the configuration of DRS boards. The most important thing is to make sure that boards of given addresses are read by correct drs machines. The file is located on supervisor in /opt/tdaq/templates/drs-crates.yml. The discovery of what boards are connected to which machines can be facilitated by running the bash script on supervisor located in /soft/drs/scripts/check_usb_boards.bash (verify!) (make sure that DRS crates are turned on during the scan).
After changing drs-crates.yml reload TDAQ config page. If there are errors while loading, the line with error will be printed. Correct the error and try reloading the page again. Then, make sure the registers of the boards are configured properly. This is more tricky. Use this elog entry for help.
When the configuration file is ready, you do not need to modify it anymore. All the further modifications will be done in the TDAQ config page. For the tests of just one crate, in the Trigger tab choose the system that trigger will be sending signals to and set the trigger rate to 100 Hz. Use the Generator for spill source and trigger source. Take a look also at the chosen DRS system tabs and make sure that it contains all DRS boards that are going to be used. Save the config, switch to main TDAQ Control page and try to initialize the system.
Problems during initialization:
- Initialization will fail if the addresses of DRS boards to be initialized do not match what is installed. Double check the machines to be queried by TDAQ and that the machines are connected to DRS boards of correct addresses.
- One can check logs on the trigger machine (in directory /tmp) and see which DRS crate returns busy
- One can visually check the problematic DRS crate and verify that LEDs on all boards go through initialization and, after it they have the same arrangement of turned on LEDs. If a DRS board has a different arrangement than others, it might not pass through the initialization/configuration process. In this case, log in to the machine connected to that board and check logs (directory /tmp)
If all the DRS boards go through the initialization, TDAQ Control should go the the READY state. Start the acquisition. The expected behavior is the "Events collected" counter should increment every virtual spill generated by the central trigger. When observing LEDs on DRS boards, the ones in second row from the top should shine (hehe) during spill time, not as bright as the other LEDs and both at the same time.
This process should be repeated for every DRS sub-system to be used during data taking. TOF-L and TOF-R/F are special cases because of one trigger line is connected from central trigger to four DRS crates through a NIM fan-in/fan-out module. In these cases the reading out problems are harder to debug because all crates should be treated as one big crate. One can temporarily skip the usage of the NIM fan module and connect trigger signals directly to the crate in question and debug it directly, but do not forget to connect the trigger signals back correctly after the investigation.
Most common problem here is the run crash due to busy
- If one of the boards is busy all the time, it might not be initialized/configured properly
- If one of the boards has busy longer than others (i.e. accepting events, but much slower than others) try restarting the crate or pull/push the board to its slot more firmly
- If there is a problem with left or right half of the crate only (constant busy or no trigger signals sent), then there may be a problem with the support module (J110 for the left side of the crate, J112 for the right side). Also, there may be a problem with central module J111 that communicates the signals wrongly with the backplane. Check the hypothesis by replacing the J11x module with the one which is confirmed to work correctly.
There are also known problems that the run continues, there is no busy, but there are no events incrementing in the "Events collected" field. The most common sources are:
- The boards may not get the eventID signal (L1 trigger line). Check the lemo cables connecting trigger box with module J111. In case of TOF-L or TOF-R/L racks check whether the NIM module fans out/in the signals to the crates
- Check the "Pending Events" grafana page whether all DRS readout machines are properly sending their collected events to events builders. If not, there may be a problem with TDAQ network (e.g. DRS readout machine has wrongly configured "-data" interface; IP, hostname, etc.)
Observe DRS Grafana page. Verify that the busy rate is everywhere the same (should be 1 or 263 us). If busy is constantly longer, the issue may be by the side of cables connecting the trigger (most probably lemo) and whether the PLLs are locked
On the same grafana page verify the status of PLL locks on the boards. Each of four DRS chips on the board has its own PLL to be locked. All boards should have locked all PLLs (four "1"s). If the values appear to be random or constantly not "1111":
- If for one DRS chip on a board: the clock signal might not properly come to the chip. A problem with DRS board - should be replaced.
- If for full DRS board - most probably a problem with the slot in DRS crate to which the board is connected.
- If for all boards in the crate - problem with backplane, with J111 controller or with differential lemo cable (white) connected to J111
- If for many crates at once - clock signal not send from the clock board - check whether the clock board is powered
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56
|
Thu, 5.02.2026 13:05:28 |
B. Maksiak | New crates + rearrangement | Four new DRS crates (Kontron-Wiener) have been delivered. They came with their own power supplies and fan units. At the same time we do not have enough of the support electronics. Some bricolage will have to be done.
It is time for some rearrangement.
Thu, 5.02.2026 13:07:51
Crates present in the experiment at the moment:
- BPD1
- BPD2 (Sandro's crate, Sandro's backplane, our power supply, Sandro's power supply is a "hostage" in Wiener lab in Meyrin)
- BPD3
- Trigger (located next to BPD3, Sandro's crate backplane, support modules)
- PSD (older version of backplane and module J110)
- TOF-L 1-4
- TOF-R 1
- TOF-R 2 (crate originally from BPD2, no power supply)
- TOF-R 3 - no crate
- TOF-R 4 - no crate
When the "hostage" power supply comes, install it to the crate from BPD2. The one which is there move to the crate TOF-R 2.
Rearrangement steps:
- Move BPD1 crate to TOF-R 3
- Move Sandro's crate at BPD2 to TOF-R 4
- Move new Kontron crate to BPD2
- Move three new Kontron crates to Counting House
Progress:
BPD1 crate moved to position TOF-R 3. Not screwed yet.
BPD2 crate (Sandro's) moved to position TOF-R 4. Not screwed yet.
One new Kontron crate (without backplane yet) moved to BPD2. Not screwed.
Three new Kontron crates moved to Counting House.
Thu, 5.02.2026 18:20:43
Took crate with serial no. 490349002 (or 490350002 ?!). Installed backplane with comment "Most probably broken". |
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55
|
Thu, 28.11.2024 20:41:24 |
D. Rybka, Y. Balkova | DRS board swapped BPD3<->TOF2 | Thu, 28.11.2024 20:42:01 DRS board 0x30C (BPD3) changed from SN112 to SN197
Fri, 29.11.2024 12:01:00 DRS board 0x416 (TOF2) changed from SN197 to SN112 |
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54
|
Mon, 25.11.2024 15:17:25 |
B. Maksiak | Beam counter signals moved from fast to slow board for fragmentation run | Due to introduction of A-detector signals, the signals from S2, S3, V0 i V1 were moved from fast board (x00f) to slow board (x00e).
S2: x00f, channel 5 -> x00e, channel 6
S3: x00f, channel 6 -> x00e, channel 7
S5: x00f, channel 7 -> x00e, channel 8
V0: x00f, channel 8 -> x00e, channel 9
V1: x00f, channel 11 -> x00e, channel 10
(channels counted from 0)
Signals from A-det were connected from trigger cables 19 and to channels 15 and 16 of x00f |
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53
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Mon, 25.11.2024 09:47:49 |
Aleksandr Dmitriev | move two MRPC boards to TOFF | | Mon, 25.11.2024 09:48:14 AD, DR: We moved x438 -> 4a0 and x43b -> 4a1 |
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52
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Wed, 30.10.2024 18:20:28 |
B. Maksiak, D. Rybka, Y. Balkova | Swapped names of BMCs of bpd2-02 and 03 | BMCs (Baseboard Management Controller) of computers bpd2-02 and bpd-03 had swapped names.
The static IP addresses in bpd20-2-bcm and bpd2-03-bcm were fixed (swapped). |
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51
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Mon, 2.10.2023 09:20:55 |
B. Maksiak | Crash of psd2 and psd4 | Mon, 2.10.2023 09:23:06
Two computers at PSD: psd2 and ps4 crashed at 2:48 last night. psd4 restarted and lost 4 GB of RAM. psd2 did not restart at all - there is no contact via ipmi. |
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50
|
Mon, 25.09.2023 17:48:16 |
B. Maksiak | Solution for falsely recognized USB ports | | Recent batch of 4xUSB 3.0 expansion cards shown a new problem. The system may see all USB ports, but only some of them may actually work and connect correctly to DRS boards. The problem can be solved by re-uploading the firmware to the Renesas chips on the USB expansion card. See this link for the solution. |
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49
|
Wed, 20.09.2023 12:12:52 |
B. Maksiak | USB 3.0 card replaced in psd1 | | psd1 computer was falsely showing 4 available USB ports. Only one port was actually communicating with the DRS board. The USB card was replaced. |
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48
|
Tue, 15.08.2023 15:18:40 |
B. Maksiak | psd1 turned off | | During data taking the psd1 computer turned off by itself. This time the computer does not want to turn back on. PSD was excluded from data taking. psd1 should be replaced. |
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47
|
Wed, 9.08.2023 11:49:49 |
B. Maksiak | Casualties during firmware upgrade | - I accidentally ripped off capacitor C483 from board SN195. It should be checked what is it responsible for.
- Board #07 cannot be programmed
- Boards SN122 and SN184 do not turn on
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46
|
Wed, 2.08.2023 19:17:16 |
B.Maksiak, Y.Balkova | New DRS firmware | New firmware revision v6 was prepared for DRS boards. Its main new features are:
- Fix problem with off-time rejection not working correctly
- Protection against event ID being duplicated
So far, the firmware of only two boards: x00f, x00e was updated. If they behave good, the rest of the boards will be updated during next MD.
Wed, 9.08.2023 19:26:51
The rest of boards were programmed. Some of them did not survive the reprogramming campaign... |
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45
|
Wed, 19.07.2023 14:54:57 |
B.Maksiak | Crash of psd1 | Last night the machine psd1 crashed and rebooted. After reboot all USB ports were visible, but DRS boards could not be contacted. Restart of the DRS crate was enough to recover the contact.
The crash resulted in losing 4 GB of RAM. One RAM stick probably got broken during the crash. It should be localized and replaced. |
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44
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Tue, 18.07.2023 16:46:18 |
B. Maksiak, P. Podlaski | Long busy problem fixed | Long busy problem has been fixed.
Two DRS registers (33 and 35) had to be zeroed explicitly.
We used Signal Tap to get full picture of how DRS board acquire data and how the DRS machine state changes its states. It was observed that the board with good busy time goes to the state DWRITE_ON quickly, while the board with bad busy time goes to state READOUT0_WAIT until it finally goes to DWRITE_ON.
A brief look in the FPGA code was enough to find that it is connected with the register s_drs_delay_readout0 which is a configurable register 33. This register, as other configurable registers should be zeroed at the initialization of the DRS board, but somehow it was not. As a result, the register was filled with a random number which was giving a delay in number of cycles defined by what was set by that random number. Explicit write of 0x0 helped.
By the way, we found a sibling register s_drs_delay_readout1 (register 35) that similarly was not being zeroed. Just in case, I write zero there too.
We made an ultimate test: stop the run, power-cycle all the DRS crates and start the run. All boards got nice 263 us busy time.
Almost two years of fighting the problem and even no firmware update was required. Such a disappointment...
We drink whisky today. |
| Attachment 1: Busy_dobry.png
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| Attachment 2: Busy_zly.png
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43
|
Mon, 17.07.2023 17:16:13 |
B.Maksiak | Wrong voltage calibration VCalib_2023-07-17_1258.bin | The DRS calibration taken about 13:00 had some issues. Boards x417, x433, x438 in runs 42292-42297 may be affected by wrong suppression.
New DRS calibration was taken. The boards mentioned above are fine now. |
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42
|
Thu, 13.07.2023 14:18:19 |
B.Maksiak | Major issue in crate TOF4 | Yesterday when testing readout I noticed that all boards in the crate TOF4 do not get eventID from the trigger system. The LED next to signal "2" on the controller (J111) was constantly shining green. TOF4 and other mRPC boards were turned off for the data taking. Only TOFF boards in TOF3 run.
I excluded the problem of trigger cables (they were providing eventID signals to oscilloscope), the problem with controller (three different controllers were checked and the situation was the same, the controller from the "bad" crate was swapped with a controller from a good crate and everything was working in the good crate and still not working in the bad crate).
Today morning I noticed that the LED of the signal "2" on the controller does not shine as long no DRS board on the right half of the TOF4 crate is connected. Plugging in any of the boards to the right side of the crate causes LED to turn on but just for like a half of full intensity.
I have checked two DRS boards from the right side of the crate (SN179/x43b, SN195/x43d) on the table whether they get eventID from ESP. They do not. On the other hand I have checked the left-most board (SN127/x430) in the same way and that one receives eventID properly.
Thu, 13.07.2023 14:29:27
Piotr checked two bad boards with the multimeter. One of them needs more current to set the pull-up resistor on pin A14 (eventID signal) than normally. This may be an indication of the burnt FPGA pin to which the pin A14 is connected. We need to check all boards from TOF4 crate in the same way.
Thu, 13.07.2023 15:42:36
All boards have been put out of the TOF4 crate. Checking them on the table.
|
SN | boardID | eventID check | electrical check
| |
SN192 | x435 | OK | <10uA | |
SN153 | x43c | OK | <10uA | |
SN149 | x434 | OK | <10uA | |
SN134 | x436 | OK | <10uA | |
SN148 | x433 | OK | <10uA | |
SN129 | x432 | OK | <10uA | |
SN128 | x431 | OK | <10uA | |
SN127 | x430 | OK | <10uA | |
SN144 | x437 | OK | <10uA | |
SN189 | x438 | Bad | 80uA | |
SN121 | x439 | OK | <10uA | |
SN122 | x43a | OK | <10uA | |
SN195 | x43d | Bad | 80uA | |
SN179 | x43b | Bad | 2mA
|
Fri, 14.07.2023 12:16:04
Higher currents on three boards correlate with the fact that the fail to receive the eventID. They are officially broken now.
Fri, 14.07.2023 15:59:43
Backplane from TOF4 (SN13) was replaced by spare backplane SN11.
Fri, 14.07.2023 16:24:56
Board x438: SN189 will be replaced by board SN152
Board x43d: SN195 will be replaced by SN173
Board x43b: SN179 will be replaced by SN176
J110: SN7
J111: SN7
J112: SN7
Fri, 14.07.2023 16:58:51
TOF4 backplane has no bad slots anymore, so the boards could be connected in their natural way.
Mon, 17.07.2023 14:58:57
TOF4 together with the rest of mRPC part of the DRS subsystem has been included back in the data taking. |
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41
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Sat, 1.07.2023 19:23:53 |
B.Maksiak | Another replacement for USB cards in tof1-01 and tof2-03 | The boards that had been replaced few days ago were showing a behavior not seen before.
They would see 4 USB ports, but none of DRS boards could connect to them. dmesg did not react while connecting DRS boards.
Sat, 1.07.2023 19:27:03
Together with Piotr, we connected USB cards to machine with Windows. None of Renesas chips was recognized.
Those two USB cards seem to be dead-on-arrival.
I replaced those cards with another two. There were no problems with them. |
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40
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Wed, 28.06.2023 09:59:35 |
B.Maksiak, Y.Balkova | DRS boards rearrangements before neutrino run | Wed, 28.06.2023 09:59:54
13 DRS boards from BPD1 were removed. Their USB cables were taken away as well and put into a box in the DRS cabinet.
Wed, 28.06.2023 15:29:27
4 additional DRS boards were removed from BPD2.
16 boards were plugged to TOF (14 for TOF mRPC + 2 for TOF-F). Additional 1 board was put to BPD3 as the slow-counter board (x00e)
DRS crates DCS control was lost for few crates (BPD1, BPD2, TOF3, TOF4). Replugging ethernet cable helped.
USB expansion cards were replaced for bpd1-03 and psd4 (old ones went to cabinet).
Wed, 28.06.2023 16:41:22
All BPD2 boards and unused BPD3 boards were taken out. All BPD computers were turned off (except of the one connected to counter boards). The boards were moved to sandbox and cabinet. |
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39
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Mon, 26.06.2023 18:12:55 |
B.Maksiak | USB 3.0 cards replaced in tof1-01 and tof2-03 | tof1-01 and tof2-03 could not show more than two USB ports. The PCI-Express USB 3.0 expansion cards were replaced there.
It looks like they were DOA (see entry 41). |
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38
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Wed, 31.05.2023 14:18:25 |
B.Maksiak | Problems before 2023 neutrino run | USB expansion cards on following computers cannot see 4 USB ports:
- bpd1-03 - three ports (board x103 cannot be contacted)
- psd4 - two ports (board x50d cannot be contacted)
- tof1-01 - two ports (x407 cannot be contacted, but one can consider plugging it to other machine)
- tof2-03 - two ports (x411 cannot be contacted, but one can consider plugging it to other machine)
Moreover, the USB cable connected from computer tof3-01 to board x426 might be malfunctioning because touching it near the board USB socket causes the board to communicate (or not) with the machine |
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37
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Wed, 23.11.2022 19:37:16 |
B. Maksiak | Board x50c (SN142) collected voltage calibration wrongly | Earlier this day I took voltage calibration. During the calibration one of DRS chips of board x50c did collected voltage calibration data improperly. All voltages gave readout at 0 ADC and sine wave gave constant readout at max ADC. It was overlooked. The voltage calibration file was propagated to DRS readout and it was used for zero suppression for most of the day. Hence, all readout from the faulty DRS chip was wrong.
I confirmed that the chip readout is fine without zero suppression and took voltage calibration again.
We need a tool to quickly verify whether voltage calibration values of freshly taken calibration run are good. |
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36
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Fri, 18.11.2022 14:40:06 |
B. Maksiak | J110 module in TOF2 replaced | | All boards connected to crate TOF2 had channel 9 sine waves missing. The faulty module was the culprit. It was replaced by new one. |
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35
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Wed, 16.11.2022 11:02:51 |
B. Maksiak | Problems with DRS boards in TOF crates | On the run meeting 15.11. I reported bad waveforms in many DRS boards from TOF crates. There were several kinds of problems:
- For many boards in TOF crates (except TOF1) the data channels showed strange waveforms.
- Several boards had strange waveforms on channel 9.
- One board had all channels from one DRS chip dead.
All the problems were being investigated during the day.
Strange data waveforms
It was found that the problem of the data channels having strange waveforms happened because the mRPC detector was already turned on and sending some signals do DRS boards making the waveforms unexpected. After turning off mRPC, the waveforms became normal.
Problems with sine waves on channels 9
Boards x405, x43b and x43c showed bad waveforms instead of sine waves on channel 9. It was discovered that the problem comes from a faulty slot of the DRS crate backplane. Shifting the boards to different slots fixed the problem. Slots were marked as faulty in the DRS database on CERNBOx.
Board x43d (SN155) has DRS3 chip dead
We decided to keep that board in the crate and remember to ignore readout of channels from that chip.
Board x43c (SN154) cannot lock PLL on chip DRS0
The board seems to not be able to lock PLL on chip DRS0 permanently. As above, we decided to keep that in mind and ignore readout of channels from that chip. |
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34
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Sun, 13.11.2022 16:52:15 |
B. Maksiak | DRS boards rearrangement in TOF | On request of mRPC group, some boards were moved in between TOF racks. TOF4 supposed to be populated by 12 boards taken from other TOF racks.
SN127: x40c (TOF1) -> x430 (TOF4)
SN128: x40b (TOF1) -> x431 (TOF4)
SN129: x40d (TOF1) -> x432 (TOF4)
SN148: x417 (TOF2) -> x433 (TOF4)
SN149: x419 (TOF2) -> x434 (TOF4)
SN192: x418 (TOF2) -> x435 (TOF4)
SN134: x414 (TOF2) -> x436 (TOF4)
SN144: x416 (TOF2) -> x437 (TOF4)
SN189: x415 (TOF2) -> x438 (TOF4)
SN121: x400 (TOF1) -> x439 (TOF4)
SN122: x401 (TOF1) -> x43a (TOF4)
SN179: x42c (TOF3) -> x43b (TOF4) |
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33
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Sat, 12.11.2022 22:59:53 |
B. Maksiak | psd4 computer lost 4 GB of RAM | | After turn off of psd computers yesterday (11.11.2022 17:30), I had to turn them on again. psd2 has 18 GB of RAM now. It should be checked. |
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32
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Sat, 12.11.2022 16:54:45 |
B. Maksiak | Rearrangement of DRS boards | DRS boards configuration was rearranged for Pb run.
Half of boards from BPD2 were taken. They populated BPD3 and ToF crates. Also, some more swapping was done in order to not use DRSv2 boards in TOF.
SN151: (Sandbox) -> x00e (BPD3)
SN152: x43d (TOF4) -> x306 (BPD3)
SN190: x309 (BPD3) -> x41a (TOF2)
SN191: x209 (BPD2) -> x41b (TOF2)
SN155: x207 (BPD2) -> x43d (TOF4)
SN#7: x208 (BPD2) -> x308 (BPD3)
SN#A: x20a (BPD2) -> x30a (BPD3)
SN#B: x20b (BPD2) -> x30b (BPD3)
SN#C: x20c (BPD2) -> x30c (BPD3)
SN#D: x20d (BPD2) -> x309 (BPD3)
SN177: x306 (BPD3) -> x41c (TOF2)
SN178: x00e (BPD3) -> x409 (TOF1) |
|
31
|
Thu, 10.11.2022 21:51:42 |
B. Maksiak | Investigation of boards 156 and 157 | This topic is connected with http://na61-elog.cern.ch/DRS+logbook/29
Boards 156 and 157 do not accept event ID signals. I analyzed their signals using Signal Tap in Quartus to see the differences of signals while new event is coming for these two boards and with two boards that do not have such problems (#06 and 151).
The signal scheme for a good board looks like the one below.

One can see that TRIGIN[0] fires the trigger on the board (drs_state comes to state TRIGGERED). L1 signal (L1_in) is lowered after busy time of the board and at the same time the event ID number comes through line TRIGIN[1].
For bad boards, the behavior is different, but not the same. Board 156 gets the main trigger signal, but TRIGIN[1] never reaches the FPGA. L1_in is permanently high. There are also no signals in the evid_receiver and uart_rx modules.

The board 157 however shows a little different behavior. TRIGIN[1] also do not reach FPGA, but L1_in looks like inactive. evid_receiver tries to decode something, but nothing comes from TRIGIN[1], so its work is pointless.

The suspicion is that something happened to the solder points of FPGA related to TRIGIN[1] pin. |
|
30
|
Thu, 10.11.2022 21:27:09 |
B. Maksiak | Boards 142, 143 moved: TOF->PSD | The boards 142 and 143 were moved back (see http://na61-elog.cern.ch/DRS+logbook/19) to PSD.
Address changes:
142: x4a1 -> x50c
143: x4a0 -> x50d
Both boards have been connected to computer psd4 |
|
29
|
Thu, 3.11.2022 14:35:04 |
B. Maksiak | Problems with board SN157 | | The board SN157 shows similar problems as board SN156. The board does not recognize event ID, produces events with number 0 and makes the DRS computer unable to send full event further to event builders. |
|
28
|
Wed, 2.11.2022 22:48:25 |
B. Maksiak | Problems with board SN188 | The board SN188 (problem observed when it had address x412) has following issues:
- When turning on the DRS crate, the board boots up very slowly. It starts booting only after all other boards finish their boot.
- When stopping the run, the communication with the board breaks and lsusb for that board gets crazy.
- When performing run, the computer with that board connected quickly increases hanging event fragments.
The board should be put out and needs diagnostics. Maybe simple reupload of firmware suffice.
Thu, 3.11.2022 16:25:04
Firmare reupload did not help, but connecting the board to other USB port did. It seems that some USB ports are more lazy than others. |
|
27
|
Tue, 1.11.2022 16:12:29 |
B. Maksiak | DRS computer bpd2-03 needs replacement | bpd2-03 machine has one RAM slot malfunctioning. That was already discovered and labeled last year, but somehow that machine still got into the machines working with DRS. I must have overlooked this. Since we have couple of spare computers, that one should be replaced.
Tue, 1.11.2022 19:01:51
The machine was replaced. It shows good amount of RAM. |
|
26
|
Mon, 19.09.2022 14:03:56 |
B. Maksiak | Problems with board SN151 | The board SN151 had problems with voltage calibration. First channel of first DRS chip seems to not react to changing DAC values when doing voltage calibration scan. Its ADC readout is always at maximum despite what voltage is fed to it. All other channels react correctly.
Tried to diagnose it. DAC chip (U107) provides correct voltage. The switch U10 gets the same voltage both on input and output. The biggest suspect was switch U8, but it appeared to behave correctly...
After the diagnosis session... everything started to work correctly. The same channel behaves good with changing input voltage (maybe its readouts are a little higher than on other channels).
Problem solved magically.
Wed, 21.09.2022 12:52:23
Well... not entirely solved, because when checking the same cold board few days later the problem happens again. The problem may be on chip U10 or U8 (both are ADV3219 multiplexer). More probably it is U10 that does not provide stable voltage as its siblings on other channels. While other chips provide stable 0V, that one goes to about -100 mV and fluctuates. A replacement would be good... |
|
25
|
Sat, 9.07.2022 11:29:21 |
B. Maksiak | munmap_chunk, double free or corruption (fixed) | During tests related to the previous entry, six machines (bpd1-0[1-4], bpd2-0[12]) were giving following errors at the first event collected after starting new run.
munmap_chunk(): invalid pointer
and/or
double free or corruption (out)
The reason why these errors appeared is right now unknown. I just stopped and shut down the properly running run, changed the margin of zero-suppression, and started new run. After the start, the first event coming caused these errors.
Next morning the error was gone as suddenly as it appeared. The source of fix is also unknown.
What things were done in the meantime:
- Restarted supervisor process on bpd1-01 computer -- didn't help
- Restarted BPD1 DRS crate -- didn't help
- Restarted bpd1-01 machine -- after restart the machine didn't see 4 USB ports, so I kept restarting it, after several unsuccessful attempts I decided to turn it off and asked shifters to take data without BPD1 and BPD2. Oskar turned on the machine next morning, we could see 4 USB ports.
- Recompiled pterodaqtyl on supervisor (compilation contained fix for the problem in previous entry)
- Changed back the config to the nominal margin of zero-suppression
What to check when the problem is back:
- Change margins of zero-suppression.
- Run data taking from pterodaqtyl installation in /soft/drs.
- Debug and localize the line in the code where the crash happens.
Wed, 13.07.2022 17:14:04 The bug has been most probably fixed!
The exact mechanism that causes the error is still not known, but there were multiple errors:
malloc(): unaligned tcache chunk detected
munmap_chunk(): invalid pointer
free(): invalid size
double free or corruption (out)
I could observe that these errors were appearing in at least two places in DRSEventProcessor and one place in DRSSubEventBuilder.
The errors could be reproduced by setting zero-suppression with very long margin_before value in JSON configuration of DRSEventProcessor. While debugging, I discovered that the non-suppressed sequence with such a long margin could overlap the region of previous sequence. Probably the module was trying to access the same fragment of memory twice (because two sequences contained some samples). An additional variable was added which prevents the next sequence to start before the place where previous sequence stops. The fix was implemented in this git commit. First tests show that the program does not crash. |
|
24
|
Sat, 9.07.2022 11:25:41 |
B. Maksiak | The readout problems (ctd.) | The problem with readout problems reported in previous entry evolved.
The problem started to be visible on every DRS board reading BPD-1 and BPD-2.
After careful tests it appeared that the problem was in the code of DRSEventProcessor that was turning on zero-suppression even when it was turned off in the JSON config.
The code was fixed, but during fixing and tests the problem in next entry appeared. |
|
23
|
Mon, 4.07.2022 15:58:30 |
B. Maksiak, K. Wójcik | Readout problems with board x20c | There is a not understandable problem happening to readout of the board x20c (#C). The board gets very noisy readout.

When the input adapters from BPD2 were disconnected, the readout waveforms stayed similar.
The board was replaced by the board 190 (ex x41a). The readout waveforms stayed similar (!).
Currently, the board 190 is being read out and the old #C is in the counting house and waiting for more careful diagnosis. |
|
22
|
Mon, 4.07.2022 15:40:03 |
B. Maksiak, K. Wójcik | Problems with boards x207, x209 | The boards x207 (#06) and x209 (#09) started to have problems with proper triggering on events. The board x209 started double triggering on the same events.
The local DRS event builder requires a particular number of event fragments (i.e. events gathered by separate DRS boards) to be present in order to build an event and send it further upstream to the DAQ event builder. The requirement is only on a number of event fragments. If there are two event fragments from the board x209 then the proper event fragment from one of other boards is missing, because the event is already built. That causes some event fragments to dangle in the memory. The memory is being filled slowly and that can be seen in both DRS grafana dashboard.
In the DRS readout dashboard it can be observed as the slope in the Event fragments in EventVectorMap plot. This may eventually cause the DRS readout computer memory overfill.

It could be also observed in the same dashboard in the panel of Triggered events on boards. 
Both boards have been replaced by the two mRPC boards: board 155 (ex. x41c) became new x207 and board 191 (ex. x41b) became new x209. After the replacement the problem is gone and there is no constant increase in the event fragments. |
|
21
|
Sat, 25.06.2022 13:27:59 |
B. Maksiak, P. Podlaski | Board 178 moved. BPD3 -> BPD3 | The board 178 was moved from serving as readout of BPD3 to the slow-counter readout board. It did not change the crate of residence.
178 changed address from x307 to x00e
x200 is connected to bpd3-4 |
|
20
|
Fri, 24.06.2022 19:19:35 |
B. Maksiak, S. Pulawski | Board 136 moved. TOF -> BPD2 | The board 136 was moved from mRPC (TOF1 crate) to BPD2
136 changed address from x409 to x200
x200 is connected to bpd2-1 |
|
19
|
Thu, 23.06.2022 11:57:37 |
B. Maksiak, B. Rumberger | Boards 142, 143 moved. PSD -> FTOF | The boards 142 and 143 were moved from PSD to FTOF.
142 changed address from x50c to x4a1
143 changed address from x50d to x4a0
The boards were inserted to crate TOF3.
x4a0 connected to tof3-03
x4a1 connected to tof3-04 |
|
18
|
Sat, 21.05.2022 20:54:59 |
B. Maksiak | Controller SN5 has issues with programming via JTAG | | It cannot program even one board due to many strange errors. |
|
17
|
Sat, 21.05.2022 17:47:18 |
B. Maksiak | Programming boards via JTAG on the controller | Programming boards using USB-Blaster connected to the controller in the crate is painful. One cannot program more than two boards at once due to many errors interrupting the programming process. The most stable way is to program one board at a time in a following way:
0. Pull out all non-DRS and non-controller boards from the crate
1. Detect all boards in the crate
2. For every single board:
a. Add Flash Device: EPCQ64
b. Add .jic file for the Flash Device
c. Click on the "Program" tick box and Start programming
d. Unclick the "Program" tick |
|
16
|
Sat, 21.05.2022 17:44:27 |
B. Maksiak | Issue with controller SN6 | The controller SN6 does not provide properly the sample clock. When inserted, the PLL-not-locked diodes in the same crate blink in a random way.
Initially it was found that one of the resistors became a tombstone, after resoldering however the issue stayed. |
|
15
|
Sat, 21.05.2022 17:41:36 |
B. Maksiak | Strange behavior of SN156 | The board SN156 behaves in a strange way. When it is put to the crate with other boards then the board overrides the readout of all boards. When doing a readout the full event consists of all boards, but all next events contain only data from board SN156. Other boards are absent in the event.
Wed, 21.09.2022 14:23:31
Diagnosis showed that the board does not receive event ID signals properly. They are 0 all the time. |
|
14
|
Fri, 29.04.2022 10:55:12 |
B. Maksiak | Problems with board x106 (SN154) | The board SN154 shows strange readouts on the first chip. It needs to be exchanged with other board.
Sun, 1.05.2022 16:22:13 (BM)
The board was replaced by the board SN153. The faulty board seems to refuse to lock its PLLs. Reprogramming of FPGA does not help. |
| Attachment 1: x106_problem.pdf
|
|
|
13
|
Fri, 25.02.2022 12:30:27 |
B. Maksiak, Y. Balkova | Plans for March and April periods | To do before shifts in March
- Change the version of PteroDAQtyl used by PSD to the one used by other systems
- Cooperate with Tobiasz towards a web interface to remotely restart Wiener crates
- What is the status of broken boards sent back to Sandro?
- What is the status of clock generators from Sandro?
Experts Shifts during March/April
Note down any kind of problems related to DRS, so it will may be useful in case of appearance of possible problems during runs
- Upload the newest firmware to the boards in PSD - on-site
- Test companion modules delivered from Pittsburgh
- J111 - bring few DRS boards, plug in J111, connect via Quartus, check if we can see/program connected DRS boards
- J110 - what is the exact role(s) of it?
- J112 - what is the exact role(s) of it?
- put modules to their crates
- Check power of BPD2/3 racks and crates
- Did they make any kind of doors to ToF racks?
- Pull cables for clock signal
- Prepare some kind of local Grafana monitoring for the condition of the boards (data taking speed, lost events, etc.)
Test period in April
- Make sure that all data taking using DRS is stable during longer runs
- Prepare a manual for shifters (e.g. what to do when some things are not working)
|
|
12
|
Mon, 6.09.2021 17:28:18 |
B. Maksiak | Preparation of DRS readout machines | | All DRS readout machines were installed and prepared. All of them are Dell blades with 24 GB of RAM and USB PCI Express expansion cards. Most of them are stored in the cage under Counting House. See this e-log entry for details. |
|
11
|
Sun, 5.09.2021 10:16:01 |
B. Maksiak | Status of PCI Express USB 3.0 cards | |
No. | Status | Location | Info
| |
1 | Mounted | PSD1
| |
2 | Mounted | PSD2
| |
3 | Mounted | PSD3
| |
4 | Mounted | PSD4
| |
5 | Mounted | BPD1-01
| |
6 | Mounted | BPD1-02
| |
7 | Mounted | BPD1-03
| |
8 | Mounted | BPD1-04
| |
9 | Mounted | BPD2-01
| |
10 | Mounted | BPD2-02
| |
11 | Mounted | BPD2-03
| |
12 | Mounted | BPD2-04
| |
13 | Mounted | BPD3-01
| |
14 | Mounted | BPD3-02
| |
15 | Mounted | BPD3-03
| |
16 | Mounted | BPD3-04
| |
17 | Mounted | TOF01 | In cage
| |
18 | Mounted | TOF02 | In cage
| |
19 | Mounted | TOF03 | In cage
| |
20 | Mounted | TOF04 | In cage
| |
21 | Mounted | TOF05 | In cage
| |
22 | Mounted | TOF06 | In cage
| |
23 | Mounted | TOF07 | In cage
| |
24 | Mounted | TOF08 | In cage
| |
25 | Mounted | TOF09 | In cage
| |
26 | Mounted | TOF10 | In cage
| |
27 | Mounted | TOF11 | In cage
| |
28 | Mounted | TOF12 | In cage
| |
29 | Mounted | TOF13 | In cage
| |
30 | Mounted | TOF14 | In cage
| |
31 | Mounted | TOF15 | In cage
| |
32 | Mounted | TOF16 | In cage
| |
33 | Mounted | TOF17 | In cage
| |
34 | Mounted | DRSPlay2 | Without metal holder
| |
35 | Mounted | EventBuilder168 |
| |
36 | Mounted | DRSPlay4 | Repaired after ripping off radiator
| |
37 | Not mounted | In cabinet | Problems with USB ports (ex-PSD1)
| |
38 | Not mounted | In cabinet | Problems with USB ports (ex BPD2-3)
| |
39 | TOF1-01 | Replacement
| |
40 | TOF2-03 | Replacement
| |
41 | Not mounted | In cabinet | Falsely available USB ports (ex-PSD1)
| |
42 | Free | In cabinet
| |
43 | Free | In cabinet
| |
44 | Free | In cabinet
| |
45 | Free | In cabinet
| |
46 | Free | In cabinet
| |
47 | Free | In cabinet
| |
48 | Free | In cabinet
| |
49 | Lost between places
| |
50 | Lost between places
| |
51 | Lost between places
| |
| Burnt | ex-DRSPlay1
|
|
|
10
|
Mon, 30.08.2021 14:24:56 |
B. Maksiak | BPD1A machine connected to TDAQ network | | Two days ago the first BPD1 readout machine was connected to TDAQ network. The network cable labeled "DRSBPD1 01" was connected to one of four Dell machines. Its hostname got the name "BPD1A". |
|
9
|
Fri, 27.08.2021 21:00:20 |
B. Maksiak | Network cables to BPDs | Yesterday and today the network cables from DAQ room to BPDs were pulled.
- 5 80-meter cables to BPD1 marked as "DRSBPD1 0[1234]" and "DRSBPD1 CTRL"
- 5 70-meter cables to BPD2 marked as "DRSBPD1 0[1234]" and "DRSBPD2 CTRL"
- 5 70-meter cables to BPD3 marked as "DRSBPD3 0[1234]" and "DRSBPD3 CTRL"
|
|
8
|
Fri, 23.07.2021 11:00:18 |
B. Maksiak | First readout from BPD1 | Yesterday we connected one DRS board to BPD1 and checked the basic connectivity and readout. Due to delay in delivery of 750 meters of network cables, we could not make the final setup of pulling data cables far to the TDAQ room. The temporal solution was to register the readout machine (na61drsbpd1) in CERN GPN and connect it using shorter cables to the nearest network socket (close to next area access doors downstream).
The readout was successful.
Fri, 23.07.2021 22:29:17
Update from one day later.
BPD1 was read out on beam triggered by S1 counter. The recorded signals are very wide. Piotr decided to borrow from PSD the slower clock module. Signals got more readable. They will be analyzed by Katowice group.
PSD got the proper trigger from Piotr. Since it includes event ID, the readout on PSD may use the non-modified pteroDRS code (the one that does not mock up the event ID by using trigger ID). PSD was set up to trigger on S1 and beam was started. We took some data. Sergey will analyze the signals. |
|
7
|
Tue, 20.07.2021 23:08:29 |
B. Maksiak | TODO | Problems
- Wiener crates have currents and voltages fluctuating
- After several thousand of events, the DRSEventBuilder stops saving files (need to change the naming convention of the output file and the way how they are being created
- The internal oscillator on new DRS boards has some glitches. One can see strange sine waves on the control plots.
|
|
6
|
Mon, 19.07.2021 09:42:09 |
Y. Balkova, B. Maksiak | Instruction for test data taking |
ssh to supervisor machine and all machines, which are used for the data taking
ssh -J drs@na61-tdaq-gwX drs@detectornumber where X is the number of the gateway
Activate virtual environment on every machine, including supervisor
source /soft/drs/venv3/bin/activate
Turn on supervisor manually on every machine, including supervisor (if not done previously)
cd /soft/drs/pteroDRS/
supervisord -c supervisor.conf -l supervisor_$(hostname).log
Start pteroDAQtyl and open logs for each machine in separate screens
cd /build/scripts/Control/
python daqinterface.py config_script_here.json
tail -f module_timestamp_here.log
Check that all modules are added correctly by looking at logs (names of logs are at the beginning of pteroDAQtyl output) and make the data taking happen
load Loading modules needed by pteroDAQtyl instance. If in logs appears "Module loaded" then it is correct.config Sending configuration to DRS boards. The from that is long, but if one can see messages like "board x<boardID> configured successfully" for every board in a given machine, then it is correct.start The main command that makes all modules running.
(in case of stop data taking)stop Gracefully stopping all modules, after that, one may start data taking againunconfig Removing configuration of modules, after that, one may configure the modules again and start back the data takingexit Exiting pteroDAQtyl process
In summary, the cycle of commands is following:load -> config -> start -> datadatadatadata -> stop -> unconfig -> exit
|
|
5
|
Sat, 17.07.2021 10:46:17 |
B. Maksiak | DRS config registers | Register 13, trigger register
0b
IGNORE DISCARD - to work without backplane and controller
0
0
0
0
0
0
x
where x:
0 - triggering turned off
1 - triggering turned on
2 - one single trigger
Note: During configuration process, one needs to set 0 at the very beginning and 1 at the very end.
Register 16, various things
0
x
double buffer on/off
ADC on/off
FX3 on/off
Register 19, calibration
0
b (bitwise!)
VCALDIS - voltage calibration (0 - turned on, 1 - turned off)
CXOE - internal oscillator switch (0 - turned off, 1 - turned on), used for timing calibration
SEL_TC - source of timing calibration switch (0 - external signal, 1 - internal oscillator)
TCAE - timing calibration (seems it is not used, TODO double-check)
SEL_CAL - calibration switch (0 - timing cal., 1 - voltage cal.)
SEL_IN - working mode (0 - calibration, 1 - input signal reading)
Examples:
For voltage calibration: 0b000010 = 0x02
For timing calibration: 0b111000 = 0x38
For data reading: 0b000001 = 0x01
Register 24, AFE in DNF
AFE triggers are internal triggers that will fire only when voltage readout on channel 1 of a given DRS chip will exceed a threshold defined in the DAC register (26). Every DRS chip on a board has its independent AFE trigger. One may define a combination of those triggers that should happen to fire the main trigger.
t0 is trigger from DRS0
t1 from DRS1
t2 from DRS2
t3 from DRS3
Let it be called the Fundamental Product (FP) of 4 variables being product of tX triggers.
FP_0 <=> 0 0 0 0 (!t3 AND !t2 AND !t1 AND !t0) (FP_0 is only true when all tX triggers are not fired)
FP_1 <=> 0 0 0 1 (!t3 AND !t2 AND !t1 AND t0) (t1-t2 triggers not fired, t3 fired)
FP_2 <=> 0 0 1 0
FP_3 <=> 0 0 1 1
FP_4 <=> 0 1 0 0
FP_5 <=> 0 1 0 1
FP_6 <=> 0 1 1 0
FP_7 <=> 0 1 1 1
FP_8 <=> 1 0 0 0
FP_9 <=> 1 0 0 1
FP_A <=> 1 0 1 0
FP_B <=> 1 0 1 1
FP_C <=> 1 1 0 0
FP_D <=> 1 1 0 1
FP_E <=> 1 1 1 0
FP_F <=> 1 1 1 1
The DNF (disjunctive normal form) logic is used to define the combination of AFE triggers. It is represented by 16 bits.
DNF 0b (FP_F)(FP_E)(FP_D)(FP_C)(FP_B)(FP_A)(FP_9)(FP_8)(FP_7)(FP_6)(FP_5)(FP_4)(FP_3)(FP_2)(FP_1)(FP_0)
DNF 0x0000: All FP_X are 0. There will be no triggers.
DNF 0x0001: Only FP_0 is activated. Main trigger will fire only when the FP_0 condition will happen.
DNF 0x0005: Fire when FP_2 and FP_0 conditions will happen.
DNF 0xAAAA: 0b 1010 1010 1010 1010, fires when: FP_1, FP_3, FP_5, FP_7, FP_9, FP_B, FP_D, FP_F (i.e. when t1 fires and doesn't care about others)
DNF 0xFFFE: 0b 1111 1111 1111 1110, fires always except when FP_0 occurs (i.e. when all triggers t0-t3 are below threshold)
DNF 0xFFFF: Fires always, even when there are no triggers t0-t3
Register 26, DACs
0
x
8
0
DAC command (see DAC documentation, table 1, page 12)
DAC address (docs, bottom right table at page 12)
X1
X2 - 12- or 16-bit (X1-X3 or X1-X4) DAC value
X3
X4
Register 25, ADCs
0
x
8
0
0
0
X1
X2
X3
X4
Bytes X1-X4 as in documentation to ADC AD9637
Register 34, delay alive for DWRITE
In clock cycles
Register 20, DRS chips configuration
0
x (hexwise)
WSR1
WSR2
0
hsamp1
hsamp2
hsamp3
(bitwise from here)
RSR reinit (0 - no, 1 - yes)
DRS on/off (0 - off, 1 - yes)
DENABLE (0 - off, 1 - on)
RMODE (0 - off, 1 - on)
keep DWRITE on (0 - no, 1 - yes)
WSR:
0b11111111 = 0xff - all channels running independently
0b01010101 = 0x55 - 2-channel cascading
0b00010001 = 0x11 - 4-channel cascading
0b00000001 = 0x01 - 8-channel cascading
hsamp - number of samples to read
0x3ff - 1024
0x1ff - 512
0x0ff - 255
etc.
Register 27, DRS chips, more configuration
0x800X00YY
X
0 - address DRS Config Register
1 - address DRS Write Shift Register (see register 20 WSR)
2 - address DRS Write Config Register
3 - disable all outputs for DRS
For different address of X, the values on Y have different meaning
See DRS documentation Table 5 for possibilities of Config Register
It was found that, in order to get rid of instabilities of sine and losing channels, one needs to write to register 27 two times with following values:
0x800000FF - in order to remind DRS to lock the PLL
0x800200FF - in order to set all channels to sample incoming data
Register 32, ADC clock pattern and delay (18 bits)
0
x
ADC delay fc0 (1)
ADC delay fc0 (2)
ADC delay dc0
ADC clock pattern (1)
ADC clock pattern (2)
Register 44 - trigger delay
The clock we consider here has 80 MHz, so one cycle is 12.5 ns. After trigger comes, the busy is active for about 250 ns. After busy, one may set additional delay to wait in number of cycles.
Example, if one needs to set 500 ns delay, then, due to 250 ns busy, an additional 250 ns of delay (20 cycles) should be set on register 44: 0x14. |
|
4
|
Tue, 13.07.2021 16:10:00 |
Y. Balkova, B. Maksiak | Rotary switches map |
Rotary switches of each DRS board have XXX format, where X can be a letter from A to F or a number from 0 to 9.
The first rotary switch of each DRS board is marking the detector where the DRS board is used and is dependent on the position of the detector on the beamline in the Z direction:
0 - beam counters
1 - BPD1
2 - BPD2
3 - BPD3
4 - TOF
5 - PSD
F - test or not yet allocated
Two rotary switches left are marking the number of the DRS board related to the given detector.
500:50A - PSD (11 boards v3)
?:? - BPD (2 boards v2)
?:? - DRS cupboard (6 boards v2)
? - MRPC (1 board v3?)
? - Bartek Maksiak (1 board v3), goes to Sandro for repairs
400:? - TOF (36 boards v3) |
|
3
|
Mon, 12.07.2021 09:39:14 |
Y. Balkova, B. Maksiak | Instruction for DRS boards |
Program FPGA
Loan programmator from Piotrek
Pin programmator to board to have target side on top
Open compiled project /Downloads/Quartus projects/T2/T2.qpf in Quartus and click "Program device"
Select programmator under Hardware Setup and select Active Serial Programming
Add device EPCQ64, select it and add file T2.pof
Tick Program/Configure and click Start
Load firmware
Switch the SW3 to boot from uC (USB)
When powered on, the D42 diode should shine yellow./fwload_fx3 cyfxflashprog.img The D42 diode should turn off
While the board is turned on (!), switch the SW3 to EEPROM./download_fx3 -t I2C -i second.img Power-cycle DRS board
Procedure in case of programming boards taken directly from Sandro
1. Put jumper on J8 and switch SW3 BOOT to SET, connect USB, power, and Blaster. Since revision 6 of FPGA firmware, put the jumper to the test pins in order to run tabletop mode.
2. Program FPGA firmware
3. Turn off power supply. Disconnect Blaster connector.
4. Turn on power supply - the D42 diode should shine yellow.
5. Program USB firmware
6. Power cycle
7. Check the front panel diodes boot sequence
8. Check the DRS board (e.g. with Wolfgang's program)
Current diode map:
-------------
T_CAL Lemo
0 1
o o
o o
2 3
4 5
o o
o o
6 7
USB
-------------
0 - not_reset (acquire) - it shines when the board is not in the reset state (i.e. for most of the time)
1 - turned on when at least one of PLLs is not locked (note: PLLs must be locked to have good readout, so the LED should be off)
2 - indicates when trigger is coming from front or backplane
3 - busy
4 - trigger enable - whether DRS is accepting triggers (register 13 set to 1)
5 - off = calibration, on = data
6 - off = timing calibration, on = voltage calibration
7 - off = timing calibration external, on = timing calibration internal |
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2
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Mon, 12.07.2021 09:22:41 |
Y. Balkova, B. Maksiak | Instruction for DRS machines | Register the machine in CERN network
MAC address --> add the machine to CERN network: network.cern.ch
During registration use name "na61drsdetector_number"
Install operating system
Piotrek --> lend pendrive with Debian (stable), install Debian without X
During installation create the user "na61drs" with password "62%idleness", for root use "********"
In BIOS change internal USB controller speed from HiSpeed to FullSpeed (lower one) in order to see all 4 USB3.0 ports (otherwise you will see 2 or 3)
Install sudo under root and add na61drs and na61tdaq to sudoerssu
apt-get install sudo
nano /etc/sudoers
#root ALL=(ALL:ALL) ALL
na61drs ALL=(ALL) NOPASSWD:ALL
na61tdaq ALL=(ALL) NOPASSWD:ALL
Install prerequisites for pterodaqtyl, for documentation see https://owyszyns.web.cern.ch/pteroDAQtyl/
Install libUSB and some useful thingscd /opt/
sudo apt-get install libssl-dev libusb-dev libusb-1.0-0 libusb-1.0-0-dev pkg-config net-tools vim tmux Add udev rules for USBcd /etc/udev/rules.d
sudo touch 50-usb-drs-rule.rules
nano 50-usb-drs-rule.rules
SUBSYSTEM=="usb", ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="00f1", MODE="0666"
sudo udevadm control --reload-rules
CMake installation (we need CMake version > 3.20sudo mkdir cmake
sudo chown na61drs:na61drs cmake/
cd cmake/
sudo apt-get install git cmake g++
wget https://github.com/Kitware/CMake/releases/download/v3.21.0-rc2/cmake-3.21.0-rc2.tar.gz
tar -xvzf cmake-3.21.0-rc2.tar.gz
cd cmake-3.21.0-rc2/
./bootstrap
make -j4
sudo make install
ZMQ installationcd /opt/
sudo mkdir zmq
sudo chown na61drs:na61drs zmq/
cd zmq/
git clone https://github.com/zeromq/libzmq.git
cd libzmq/
mkdir build
cd build
cmake ..
make -j4
sudo make install
cd ../..
git clone https://github.com/zeromq/cppzmq.git
cd cppzmq/
mkdir build
cd build
cmake ..
make -j4
sudo make install
Install and configure Supervisorsudo apt-get install supervisor
sudo apt-get install python-pip
sudo pip install supervisor_twiddler
sudo nano /etc/supervisor/supervisord.conf
[inet_http_server]
port=*:9001
[rpcinterface:twiddler]
supervisor.rpcinterface_factory = supervisor_twiddler.rpcinterface:make_twiddler_rpcinterface
[group:daq]
sudo systemctl restart supervisor
sudo systemctl status supervisor
Pterodaqtyl installationcd
git clone https://gitlab.cern.ch/na61-software/online/pterodaqtyl/pterodaqtyl.git
cd pterodaqtyl/
git submodule init src/Modules/drsmodules
git submodule update src/Modules/drsmodules
cd src/Modules/drsmodules
git checkout master
git pull
cd ../../..
git submodule init src/Utilities/drsutilities
git submodule update src/Utilities/drsutilities
git checkout master
git pull
cd ../../..
mkdir build
cd build
cmake ..
make -j4
Install things necessary for monitoringsudo apt-get install python3-pip
sudo pip3 install jsonschema
sudo pip3 install zmq |
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Sat, 10.07.2021 12:17:37 |
B. Maksiak, Y. Balkova | Adventures with DRS machines | The first machine that we tried to set up was an ex-ALICE HP ProLiant DL160 G6. After the installation of PCI-E USB 3.0 card, it appeared that the machine sees only three out of four USB 3.0 ports.
After 1.5 days of struggling, which involved:
- Trying other machine
- Trying other PCI-E card (one was burned)
- Trying many options in BIOS
we decided to try with another machine, Dell XS23-TY3, which was supposed to be a part of Oskar's event builder.
The machine, after installation of PCI-E card, showed 4 USB ports ONLY when in BIOS we changed internal USB controller speed from HiSpeed to FullSpeed (to the lower speed).
The machine name is na61drsplay2 and is registered to BM. |
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